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datasheet 5p49v5943 march 3, 2017 1 ?2017 integrated device technology, inc. programmable clock generator 5p49v5943 description the 5p49v5943 is a programmable clock generator intended for high performance consumer, networking, industrial, computing, and data-com munications applications. configurations may be stored in on-chip one-time programmable (otp) memory or changed using i 2 c interface. this is idts fifth generation of programmable clock technology (versaclock ? 5). the frequencies are generated from a single input reference clock. two select pins allow up to 4 different configurations to be programmed and accessible using processor gpios or bootstrapping. the different selections may be used for different operating modes (full function, partial function, partial power-down), regional standar ds (us, japan, europe) or system production margin testing. the device may be configured to use one of two i 2 c addresses to allow multiple de vices to be used in a system. pin assignment features ? generates up to two independent output frequencies ? high performance, low phase noise pll, <0.7 ps rms typical phase jitter on outputs: ? pcie gen1, 2, 3 comp liant clock capability ? usb 3.0 compliant clock capability ? 1 gbe and 10 gbe ? two fractional output dividers (fods) ? independent spread spectrum capability on each output pair ? four banks of internal non-volatile in-system programmable or factory programmable otp memory ? i 2 c serial programming interface ? one reference lvcmos output clock ? two universal output pairs: ? each configurable as one differential output pair or two lvcmos outputs ? i/o standards: ? single-ended i/os: 1.8v to 3.3v lvcmos ? differential i/os - lvpecl, lvds and hcsl ? input frequency ranges: ? lvds, lvpecl, hcsl differential clock input (clkin, clkinb) ? 1mhz to 350mhz ? output frequency ranges: ? lvcmos clock outputs ? 1mhz to 200mhz ? lvds, lvpecl, hcsl differential clock outputs ? 1mhz to 350mhz ? individually selectable output voltage (1.8v, 2.5v, 3.3v) for each output pair ? programmable loop bandwidth ? programmable output to output skew ? programmable slew rate control ? individual output enable/disable ? power-down mode ? 1.8v, 2.5v or 3.3v core v ddd , v dda ? available in 20-pin vfqfpn 3mm x 3mm package ? -40 to +85c industrial temperature operation 1 6 20-pin vfqfpn gnd clkin out1 clkinb gnd out1b v ddo 1 v dda sd/oe sel1/sda sel0/scl v ddo 2 out2 out2b gnd v ddd v ddo 0 out0_sel_i2cb epad 2 3 4 5 7 8 910 11 12 13 14 15 16 17 18 19 20 v dd gnd
programmable cl ock generator 2 march 3, 2017 5p49v5943 datasheet functional block diagram applications ? ethernet switch/router ? pci express 1.0/2.0/3.0 ? broadcast video/audio timing ? multi-function printer ? processor and fpga clocking ? any-frequency clock conversion ? msan/dslam/pon ? fiber channel, san ? telecom line cards ? 1 gbe and 10 gbe clkin clkinb sd/oe sel1/sda sel0/scl v dda v ddd v ddo 0 out0_sel_i2cb v ddo 1 out1 out1b v ddo 2 out2 out2b fod1 fod2 pll otp and control logic
march 3, 2017 3 programmable clock generator 5p49v5943 datasheet table 1: pin descriptions number name description 1 clkin input pull-down differential clock input. weak 100kohms internal pull-down. 2 clkinb input pull-down complementary differential clock input. weak 100kohms internal pull-down. 3 vdda power analog functions power supply pin. connect to 1.8v to 3.3v. vdda and vddd should have the same voltage applied. 4 vdd power power supply pin. connect to 1.8 to 3.3v. 5 sd/oe input pull-down enables/disables the outputs (oe) or powers down the chip (sd). the sh bit controls the configuration of the sd/oe pin. the sh bit needs to be high for sd/oe pin to be configured as sd. the sp bit (0x02) controls the polarity of the signal to be either active high or low only when pin is configured as oe (default is active low.) weak internal pull down resistor. when configured as sd, device is shut down, differential outputs are driven high/low, and the single- ended lvcmos outputs are driven low. when configured as oe, and outputs are disabled, the outputs can be selected to be tri-stated or driven high/low, depending on the programming bits as shown in the sd/oe pin function truth table. 6 sel1/sda input pull-down configuration select pin, or i2c sda input as selected by out0_sel_i2cb. weak internal pull down resistor. 7 sel0/scl input pull-down configuration select pin, or i2c scl input as selected by out0_sel_i2cb. weak internal pull down resistor. 8 vddo2 power output power supply. connect to 1.8 to 3.3v. sets output voltage levels for out2/out2b. 9 out2 output output clock 2. please refer to the output drivers section for more details. 10 out2b output complementary output clock 2. please refer to the output drivers section for more details. 11 gnd power connect to ground. 12 gnd power connect to ground. 13 out1b output complementary output clock 1. please refer to the output drivers section for more details. 14 out1 output output clock 1. please refer to the output drivers section for more details. 15 vddo1 power output power supply. connect to 1.8 to 3.3v. sets output voltage levels for out1/out1b. 16 gnd power connect to ground. 17 vddd power digital functions power supply pin. connect to 1.8 to 3.3v. vdda and vddb should have the same voltage applied. 18 gnd power connect to ground. 19 vddo0 power power supply pin for out0_sel_i2cb. connect to 1.8 to 3.3v. sets output voltage levels for out0. 20 out0_selb_i2c input/output pull-down latched input/lvcmos output. at power up, the voltage at the pin out0_sel_i2cb is latched by the part and used to select the state of pins 8 and 9. if a weak pull up (10kohms) is placed on out0_sel_i2cb, pins 8 and 9 will be configured as hardware select pins, sel1 and sel0. if a weak pull down (10kohms) is placed on out0_sel_i2cb or it is left floating, pins 8 and 9 will act as the sda and scl pins of an i2c interface. after power up, the pin acts as a lvcmos reference output. epad power connect to ground pad. type
programmable cl ock generator 4 march 3, 2017 5p49v5943 datasheet pll features and descriptions spread spectrum to help reduce electromagnet ic interference (emi), the 5p49v5943 supports spread spectrum modulation. the output clock frequencies can be modulated to spread energy across a broader range of frequencies, lowering system emi. the 5p49v5943 implements spread spectrum using the fractional-n output divide, to achieve controllable modulation rate and spreading magnitude. the spread spectrum can be applied to any output clock, any clock frequency, and any spread amount from 0.25% to 2.5% center spread and -0.5% to -5% down spread. table 2: loop filter pll loop bandwidth range depends on the input reference frequency (fref) and can be set between the loop bandwidth range as shown in the table below. table 3: configuration table this table shows the sel1, sel0 settings to select the configuration stored in otp. four configurations can be stored in otp. these can be factory programmed or user programmed. at power up time, the sel0 and sel1 pins must be tied to either the vddd/vdda power supp ly so that they ramp with that supply or are tied low (thi s is the same as floating the pins). this will cause the regist er configuration to be loaded that is selected according to table 3 above. providing that out0_sel_i2cb was 1 at por an d otp register 0:7=0, after the first 10ms of operation the levels of the selx pins can be changed, either to low or to the same level as vddd/vdda. the selx pins must be driven with a digital signal of < 300ns rise/fall time and only a single pin can be changed at a time. after a pin level change, the device must not be interrupted for at least 1ms so that the new values have time to load and take effect. if out0_sel_i2cb was 0 at por, alternate configurations can only be loaded via the i2c interface. input reference frequency?fref (mhz) loop bandwidth min (khz) loop bandwidth max (khz) 1 40 126 350 300 1000 out0_sel_i2cb @ por sel1 sel0 i 2 c access reg0:7 config 100no00 101no01 110no02 111no03 0 x x yes 1 i2c defaults 0xxyes00
march 3, 2017 5 programmable clock generator 5p49v5943 datasheet reference clock input pins the 5p49v5943 supports one reference clock input. the clock input (clkin, clkinb) is a fully differential input that only accepts a reference clock. the differential input accepts differential clocks from all the differential logic types and can also be driven from a single ended clock on one of the input pins. otp interface the 5p49v5943 can also store its configuration in an internal otp. the contents of the device's internal programming registers can be saved to the otp by setting burn_start (w114[3]) to high and can be loaded back to the internal programming registers by setting usr_rd_start(w114[0]) to high. to initiate a save or restore using i 2 c, only two bytes are transferred. the device address is issued with the read/write bit set to ?0?, followed by the appropriate command code. the save or restore instruction executes after the stop condition is issued by the master, during which time the 5p49v5943 will not generate acknowledge bits. the 5p49v5943 will acknowledge the instructions after it has completed execution of them. during that time, the i 2 c bus should be interpreted as busy by all other users of the bus. on power-up of the 5p49v5943, an automatic restore is performed to load the otp contents into the internal programming registers. the 5p49v5943 will be ready to accept a programming instruction once it acknowledges its 7-bit i 2 c address. availability of prim ary and secondary i 2 c addresses to allow programming for multiple devices in a system. the i 2 c slave address can be changed from the default 0xd4 to 0xd0 by programming the i2c_addr bit d0. versaclock 5 programming guide provides detailed i 2 c programming guidelines and register map. sd/oe pin function the polarity of the sd/oe signal pin can be programmed to be either active high or low with the sp bit (w16[1]). when sp is ?0? (default), the pin becomes active low and when sp is ?1?, the pin becomes active high. the sd/oe pin can be configured as either to shutdown the pll or to enable/disable the outputs. the sh bit controls the configuration of the sd/oe pin the sh bit needs to be high for sd/oe pin to be configured as sd . when configured as sd, device is shut down, differential outputs are driven high/low, and the single-ended lvcmos outputs are driven low. when configured as oe, and outputs are disabled, the output s are driven high/low. table 4: sd/oe pin fu nction truth table output alignment each output divider block has a synchronizing por pulse to provide startup alignment bet ween outputs. this allows alignment of outputs for low skew performance. the phase alignment works both for integer output divider values and for fractional output divider values. besides the por at power up, th e same synchronization reset is also triggered when switching between configurations with the sel0/1 pins. this ensures that the outputs remain aligned in every configuration. this reset causes the outputs to suspend for a few hundred microseconds so the switchover is not glitch-less. the reset can be disabled for applications where glitch-less switch over is required and alignment is not critical. when using i 2 c to reprogram an output divider during operation, alignment can be lost. alignment can be restored by manually triggering the reset through i 2 c. when alignment is required for outputs with different frequencies, the outputs are ac tually aligned on the falling edges of each output by defau lt. rising edge alignment can also be achieved by utilizing the programmable skew feature to delay the faster clock by 180 degrees. the programmable skew feature also allows for fine tuning of the alignment. for details of register programming, please see versaclock 5 family register descriptio ns and programming guide for details. sd/oe input sp sh oen osn global shutdown outn sh bit sp bit osn bit oen bit sd/oe outn 0 0 0 x x tri-state 2 0 0 1 0 x output active 0 0 1 1 0 output active 0 0 1 1 1 output driven high low 0 1 0 x x tri-state 2 0 1 1 0 x output active 0 1 1 1 0 output driven high low 0 1 1 1 1 output active 1 0 0 x 0 tri-state 2 1 0 1 0 0 output active 1 0 1 1 0 output active 1 1 0 x 0 tri-state 2 1 1 1 0 0 output active 1 1 1 1 0 output driven high low 1x x x 1 output driven high low 1 note 1 : global shutdown note 2 : tri-state regardless of oen bits
programmable cl ock generator 6 march 3, 2017 5p49v5943 datasheet output divides each of the four output divides are comprised of a 12-bit integer counter, and a 24-bit fractional counter. the output divide can operate in integer divide only mode for improved performance, or utilize the fracti onal counters to generate any frequency with a synthesis accuracy better than 50ppb. the output divide al so has the capabilit y to apply a spread modulation to the output freq uency. independent of output frequency, a triangle wave modulation between 30 and 63khz may be generated. output skew for outputs that share a common output divide value, there will be the ability to skew output s by quadrature values to minimize interaction on the pcb. the skew on each output can be adjusted from 0 to 360 degrees. skew is adjusted in units equal to 1/32 of the vco period. so, for 100 mhz output and a 2800 mhz vco, you can select how many 11.161ps units you want added to your skew (resulting in units of 0.402 degrees). for example, 0, 0.402, 0.804, 1.206, 1.408, and so on. the granularity of the skew adjustment is always dependent on the vco period and the output period. output drivers the out1 to out2 clock outputs are provided with register-controlled output drivers. by selecting the output drive type in the appropriate regist er, any of these outputs can support lvcmos, lvpecl, hcsl or lvds logic levels the operating voltage ranges of each output is determined by its independent output power pin (v ddo ) and thus each can have different output voltage leve ls. output voltage levels of 2.5v or 3.3v are supported for differential hcsl, lvpecl operation, and 1. 8v, 2.5v, or 3.3v are supported for lvcmos and differential lvds operation. each output may be enabled or disabled by register bits. when disabled an output will be in a logic 0 state as determined by the programming bit table shown on page 6. lvcmos operation when a given output is configur ed to provide lvcmos levels, then both the outx and outx b outputs will toggle at the selected output frequency. all the previously described configuration and control apply equally to both outputs. frequency, phase alignment, voltage levels and enable / disable status apply to both the outx and outxb pins. the outx and outxb outputs can be selected to be phase-aligned with each other or inverted relative to one another by register programming bits. selection of phase-alignment may have negative effects on the phase noise performance of any part of the device due to increased simultaneous switching noise within the device. device hardware configuration the 5p49v5943 supports an internal one-time programmable (otp) memory that can be pre-programmed at the factory with up to 4 complete device configuration. these configurations can be over-written using the serial interface once reset is complete . any configuration written via the programming interface needs to be re-written after any power cycle or reset. please contact idt if a specific factory-programmed configuration is desired. device start-up & reset behavior the 5p49v5943 has an internal power-up reset (por) circuit. the por circuit will remain acti ve for a maximum of 10ms after device power-up. upon internal por circuit expi ring, the device will exit reset and begin self-configuration. the device will load internal registers according to ta b l e 3 . once the full confi guration has been loaded, the device will respond to accesses on the serial port and will attempt to lock the pll to the selected source and begin operation. power up ramp sequence vdda and vddd must ramp up together. vddo0~2 must ramp up before, or concurrently with, vdda and vddd. all power supply pins must be connected to a power rail even if the output is unused. all power supplies must ramp in a linear fashion and ramp monotonically. vddo0~2 vdda vddd
march 3, 2017 7 programmable clock generator 5p49v5943 datasheet i 2 c mode operation the device acts as a slave device on the i 2 c bus using one of the two i 2 c addresses (0xd0 or 0xd4) to allow multiple devices to be used in the system. the interface accepts byte-oriented block write and block read operations. two address bytes specify the register address of the byte position of the first register to write or read. data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first). read and write block transfers can be stopped after any complete byte transfer. during a write operation, data will not be moved into the registers until the stop bit is received, at wh ich point, all data received in the block write will be wr itten simultaneously. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-down resistors ha ve a size of 100k ? typical. i 2 c slave read and write cycle sequencing current ? read s dev ? addr ? + ? r a data ? 0 a data ? 1 a a data ? n abar p sequential ? read s dev ? addr ? + ? w a data ? 0 a data ? 1 a a data ? n abar p reg ? start ? addr a sr dev ? addr ? + ? r a sequential ? write s dev ? addr ? + ? w a data ? 0 p a data ? 1 a a data ? n a from ? master ? to ? slave from ? slave ? to ? master reg ? start ? addr a s ? = ? start sr ? = ? repeated ? start a ? = ? acknowledge abar= ? none ? acknowledge p ? = ? stop
programmable cl ock generator 8 march 3, 2017 5p49v5943 datasheet table 5: i 2 c bus dc characteristics table 6: i 2 c bus ac characteristics note 1: a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih (min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 2: i2c inputs are 5v tolerant. symbol parameter conditions min typ max unit vih input high level for sel1/sda pin and sel0/scl pin. 0.7xvddd 5.5 2 v vil input low level for sel1/sda pin and sel0/scl pin. gnd-0.3 0.3xvddd v vhys hysteresis of inputs 0.05xvddd v iin input leakage current -1 30 a vol output low voltage iol = 3 ma 0.4 v symbol parameter min typ max unit fsclk serial clock frequency (scl) 10 400 khz tbuf bus free time between stop and start 1.3 s tsu:start setup time, start 0.6 s thd:start hold time, start 0.6 s tsu:data setup time, data input (sda) 0.1 s thd:data hold time, data input (sda) 1 0 s tovd output data valid from clock 0.9 s cb capacitive load for each bus line 400 pf tr rise time, data and clock (sda, scl) 20 + 0.1xcb 300 ns tf fall time, data and clock (sda, scl) 20 + 0.1xcb 300 ns thigh high time, clock (scl) 0.6 s tlow low time, clock (scl) 1.3 s tsu:stop setup time, stop 0.6 s
march 3, 2017 9 programmable clock generator 5p49v5943 datasheet table 7: absolute maximum ratings stresses above the ratings listed below can cause permanent dama ge to the 5p49v5943. these ratings, which are standard values f or idt commercially rated parts, are stress ratings only. functional oper ation of the device at these or any other conditions above th ose indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended peri ods can affect product reliability. electrical parameters are guarante ed only over the recommended operating temperature range. table 8: recommended operation conditions note: v ddo 1, v ddo 2, v ddo 3, and v ddo 4 must be powered on either before or simultaneously with v ddd , v dda and v ddo 0. item rating supply voltage, v dda, v ddd, v ddo 3.465v inputs clkin, clkinb other inputs 0v to 1.2v voltage swing single-ended -0.5v to v ddd outputs, v ddo (lvcmos) -0.5v to v ddo + 0.5v outputs, i o (sda) 10ma package thermal impedance, ? ja 42 ? c/w (0 mps) package thermal impedance, ? jc 41.8 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c esd human body model 2000v junction temperature 125c symbol parameter min typ max unit v ddox power supply voltage for supporting 1.8v outputs 1.71 1.8 1.89 v v ddox power supply voltage for supporting 2.5v outputs 2.375 2.5 2.625 v v ddox power supply voltage for supporting 3.3v outputs 3.135 3.3 3.465 v v ddd power supply voltage fo r core logic functions 1.71 3.465 v v dda analog power supply voltage. use filtered analog power supply. 1.71 3.465 v t a operating temperature, ambient -40 +85 c c load_out maximum load capacitance (3.3v lvcmos only) 15 pf f in external reference clock clkin, clkinb 5350mhz t pu power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 5 ms
programmable cloc k generator 10 march 3, 2017 5p49v5943 datasheet table 9: input capacitance, lvcmos outp ut impedance, and internal pull-down resistance (t a = +25 c) table 10: dc electri cal characteristics table 11: electrical characteristics ? differential clock input parameters 1,2 (supply voltage v dda , v ddd , v ddo 0 = 3.3v 5%, 2.5v 5%, 1.8v 5%, ta = -40c to +85c) 1. guaranteed by design and characteri zation, not 100% tested in production. 2. slew rate measured through 75mv win dow centered around differential zero. symbol parameter min typ max unit cin input capacitance (clkin, clkinb, sd/oe, sel1/sda, sel0/scl) 37pf pull-down resistor sd/oe, sel1/sda, sel0/scl, clkin, clkinb, out0_sel_i2cb 100 300 k ? rout lvcmos output driver impedance (vddo = 1.8v, 2.5v, 3.3v) 17 ? symbol parameter test conditions min typ max unit iddcore 3 core supply current 100 mhz on all outputs, 25 mhz refclk 30 34 ma lvpecl, 350 mhz, 3.3v vddox 42 47 ma lvpecl, 350 mhz, 2.5v vddox 37 42 ma lvds, 350 mhz, 3.3v vddox 18 21 ma lvds, 350 mhz, 2.5v vddox 17 20 ma lvds, 350 mhz, 1.8v vddox 16 19 ma hcsl, 250 mhz, 3.3v vddox, 2 pf load 29 33 ma hcsl, 250 mhz, 2.5v vddox, 2 pf load 28 33 ma lvcmos, 50 mhz, 3.3v, vddox 1,2 16 18 ma lvcmos, 50 mhz, 2.5v, vddox 1,2 14 16 ma lvcmos, 50 mhz, 1.8v, vddox 1,2 12 14 ma lvcmos, 200 mhz, 3.3v vddox 1 36 42 ma lvcmos, 200 mhz, 2.5v vddox 1,2 27 32 ma lvcmos, 200 mhz, 1.8v vddox 1,2 16 19 ma iddpd power down current sd asserted, i2c programming 10 14 ma 1. single cmos driver active. 2. measured into a 5? 50 ohm trace with 2 pf load. 3. iddcore = idda+ iddd, no loads. iddox output buffer supply current symbol parameter test conditions min typ max unit vih input high voltage - clkin, clkin b single-ended input 0.55 1.7 v vil input low voltage - clkin, clkinb single-ended input gnd - 0.3 0.4 v vswing input amplitude - clkin, clkinb peak to peak value, single-ended 200 1200 mv dv/dt input slew rate - clkin, clkinb measured differentially 0.4 8 v/ns iil input leakage low current vin = gnd -5 5 a iih input leakage high current vin = 1.7v 20 a dtin input duty cycle measurement from differential waveform 45 55 %
march 3, 2017 11 progra mmable clock generator 5p49v5943 datasheet table 12: dc electrical chara cteristics for 3.3v lvcmos (v ddo = 3.3v5%, ta = -40c to +85c) 1 1. see ?recommended operating conditions? table. table 13: dc electrical chara cteristics for 2.5v lvcmos (v ddo = 2.5v5%, ta = -40c to +85c) table 14: dc electrical char acteristics for 1.8v lvcmos (v ddo = 1.8v5%, ta = -40c to +85c) symbol parameter test conditions min typ max unit voh output high voltage ioh = -15ma 2.4 vddo v vol output low voltage iol = 15ma 0.4 v iozdd output leakage current (out1~4) tri-state outputs, vddo = 3.465v 5a iozdd output leakage current (out0) tri-state outputs, vddo = 3.465v 30 a vih input high voltage single-ended inputs - sd/oe 0.7xvddd vddd + 0.3 v vil input low voltage single-ended inputs - sd/oe gnd - 0.3 0.3xvddd v vih input high voltage single-ended input out0_sel_i2cb 2vddo0 + 0.3v vil input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v t r /t f input rise/fall time sd/oe, sel1/sda, sel0/scl 300 ns symbol parameter test conditions min typ max unit voh output high voltage ioh = -12ma 0.7xvddo v vol output low voltage iol = 12ma 0.4 v iozdd output leakage current (out1~4) tri-state outputs, vddo = 2.625v 5a iozdd output leakage current (out0) tri-state outputs, vddo = 2.625v 30 a vih input high voltage single-ended inputs - sd/oe 0.7xvddd vddd + 0.3 v vil input low voltage single-ended inputs - sd/oe gnd - 0.3 0.3xvddd v vih input high voltage single-ended input out0_sel_i2cb 1.7 vddo0 + 0.3 v vil input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v t r /t f input rise/fall time sd/oe, sel1/sda, sel0/scl 300 ns symbol parameter test conditions min typ max unit voh output high voltage ioh = -8ma 0.7 xvddo vddo v vol output low voltage iol = 8ma 0.25 x vddo v iozdd output leakage current (out1~4) tri-state outputs, vddo = 3.465v 5a iozdd output leakage current (out0) tri-state outputs, vddo = 3.465v 30 a vih input high voltage single-ended inputs - sd/oe 0.7 * vddd vddd + 0.3 v vil input low voltage single-ended inputs - sd/oe gnd - 0.3 0.3 * vddd v vih input high voltage single-ended input out0_sel_i2cb 0.65 * vddo0 vddo0 + 0.3 v vil input low voltage single-ended input out0_sel_i2cb gnd - 0.3 0.4 v t r /t f input rise/fall time sd/oe, sel1/sda, sel0/scl 300 ns
programmable cloc k generator 12 march 3, 2017 5p49v5943 datasheet table 15: dc electrical characteristics for lvds (v ddo = 3.3v+ 5% or 2.5v+ 5%, ta = -40c to +85c) table 16: dc electrical ch aracteristics for lvds (v ddo = 1.8v+ 5%, ta = -40c to +85c) symbol parameter min typ max unit v ot (+) differential output voltage for the true binary state 247 454 mv v ot (-) differential output voltage for the false binary state -247 -454 mv v ot change in v ot between complimentary output states 50 mv v os output common mode voltage (offset voltage) 1.125 1.25 1.375 v v os change in v os between complimentary output states 50 mv i os outputs short circuit current, v out + or v out - = 0v or v ddo 924ma i osd differential outputs short circuit current, v out + = v out - 612ma symbol parameter min typ max unit v ot (+) differential output voltage for the true binary state 247 454 mv v ot (-) differential output voltage for the false binary state -247 -454 mv v ot change in v ot between complimentary output states 50 mv v os output common mode voltage (offset voltage) 0.8 0.875 0.95 v v os change in v os between complimentary output states 50 mv i os outputs short circuit current, v out + or v out - = 0v or v ddo 924ma i osd differential outputs short circuit current, v out + = v out - 612ma
march 3, 2017 13 progra mmable clock generator 5p49v5943 datasheet table 17: dc electrical ch aracteristics for lvpecl (v ddo = 3.3v+ 5% or 2.5v+ 5%, ta = -40c to +85c) table 18: electrical characteristics ? dif 0.7v low power hcsl differential outputs (v ddo = 3.3v5%, 2.5v5%, ta = -40c to +85c) 1. guaranteed by design and characteri zation. not 100% tested in production 2. measured from differential waveform. 3. slew rate is measured through the v swing voltage range centered around differential 0v . this results in a +/-150mv window around differential 0v. 4. v cross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential rising edge (i.e. clock rising and clock# falling). 5. the total variation of all v cross measurements in any particular system . note that this is a subset of v cross min/max (v cross absolute) allowed. the intent is to limit v cross induced modulation by setting ? v cross to be smaller than v cross absolute. 6. measured from single-ended waveform. 7. measured with scope averaging off, using statistics fu nction. variation is difference between min. and max. symbol parameter min typ max unit v oh output voltage high, terminated through 50 ? tied to v dd - 2 v v ddo - 1.19 v ddo - 0.69 v v ol output voltage low, terminated through 50 ? tied to v dd - 2 v v ddo - 1.94 v ddo - 1.4 v v swing peak-to-peak output voltage swing 0.55 0.993 v symbol parameter conditions min typ max units notes dv/dt slew rate scope averaging on 1 4 v/ns 1,2,3 dv/dt slew rate scope averaging on 20 % 1,2,3 vhigh voltage high 660 850 mv 1,6,7 vlow voltage low -150 150 mv 1,6 vmax maximum voltage 1150 mv 1 vmin minimum voltage -300 mv 1 vswing voltage swing scope averaging off 300 mv 1,2,6 vcross crossing voltage value scope averaging off 250 550 mv 1,4,6 vcross crossing voltage variation scope averaging off 140 mv 1,5 statistical measurement on single-ended signal using oscilloscope math function (scope averaging on) measurement on single-ended signal using absolute value (scope averaging off)
programmable cloc k generator 14 march 3, 2017 5p49v5943 datasheet table 19: ac timing elec trical characteristics (v ddo = 3.3v+5% or 2.5v+5% or 1.8v 5%, ta = -40c to +85c) (spread spectrum generation = off) symbol parameter test conditions min. typ. max. units fin 1 input frequency input frequency limit (clkin, clkinb) 1350mhz single ended clock output limit (lvcmos) 1200 differential cock output limit (lvpecl/ lvds/hcsl) 1350 fvco vco frequency vco operating frequency range 2600 2900 mhz fpfd pfd frequency pfd operating frequency range 1 1 150 mhz fbw loop bandwidth input frequency = 25mhz 0.06 0.9 mhz t2 input duty cycle duty cycle 45 50 55 % measured at vdd/2, all outputs except reference output out0, vddox= 2.5v or 3.3v 45 50 55 % measured at vdd/2, all outputs except reference output out0, vddox=1.8v 40 50 60 % measured at vdd/2, reference output out0 (5mhz - 120mhz) with 50% duty cycle input 40 50 60 % measured at vdd/2, reference output out0 (150.1mhz - 200mhz) with 50% duty cycle input 30 50 70 % slew rate, slew[1:0] = 00 1.0 2.2 slew rate, slew[1:0] = 01 1.2 2.3 slew rate, slew[1:0] = 10 1.3 2.4 slew rate, slew[1:0] = 11 1.7 2.7 slew rate, slew[1:0] = 00 0.6 1.3 slew rate, slew[1:0] = 01 0.7 1.4 slew rate, slew[1:0] = 10 0.6 1.4 slew rate, slew[1:0] = 11 1.0 1.7 slew rate, slew[1:0] = 00 0.3 0.7 slew rate, slew[1:0] = 01 0.4 0.8 slew rate, slew[1:0] = 10 0.4 0.9 slew rate, slew[1:0] = 11 0.7 1.2 rise times lvds, 20% to 80% 300 fall times lvds, 80% to 20% 300 rise times lvpecl, 20% to 80% 400 fall times lvpecl, 80% to 20% 400 output duty cycle single-ended 3.3v lvcmos output clock rise and fall time, 20% to 80% of vddo (output load = 5 pf) vddox=3.3v single-ended 2.5v lvcmos output clock rise and fall time, 20% to 80% of vddo (output load = 5 pf) vddox=2.5v single-ended 1.8v lvcmos output clock rise and fall time, 20% to 80% of vddo (output load = 5 pf) vddox=1.8v t4 2 v/ns mhz t5 ps fout output frequency t3 5
march 3, 2017 15 progra mmable clock generator 5p49v5943 datasheet cycle-to-cycle jitter (peak-to-peak), multiple output frequencies switching, differential outputs (1.8v to 3.3v nominal output voltage) out0=25mhz out1=100mhz out2=125mhz out3=156.25mhz 46 ps cycle-to-cycle jitter (peak-to-peak), multiple output frequencies switching, lvcmos outputs (1.8 to 3.3v nominal output voltage) out0=25mhz out1=100mhz out2=125mhz out3=156.25mhz 74 ps rms phase jitter (12khz to 5mhz integration range) reference clock (out0), 25 mhz lvcmos outputs (1.8 to 3.3v nominal output voltage). out0=25mhz out1=100mhz out2=125mhz out3=156.25mhz 0.5 ps rms phase jitter (12khz to 20mhz integration range) differential output, vddo = 3.465v, 25mhz input, 156.25mhz output frequency out0=25mhz out1=100mhz out2=125mhz out3=156.25mhz 0.75 1.5 ps t7 output skew skew between the same frequencies, with outputs using the same driver format and phase delay set to 0 ns. 75 ps t8 3 startup time pll lock time from power-up, measured after all vdd's have raised above 90% of their target value. 10 ms t9 4 startup time pll lock time from shutdown mode 34ms 1. practical lower frequency is determined by loop filter settings. 2. a slew rate of 2.75v/ns or greater should be selected for output frequencies of 100mhz or higher. 3. includes loading the configuration bits from eprom to pll registers. it does not include eprom programming/write time. 5. duty cycle is only guaranteed at max slew rate settings. 4. actual pll lock time depends on the loop configuration. t6 clock jitter
programmable cloc k generator 16 march 3, 2017 5p49v5943 datasheet table 20: pci express jitter specifications (v ddo = 3.3v+ 5% or 2.5v+ 5%, t a = -40c to +85c) note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. t he device will meet specificati ons after thermal equilibrium has been reached under these conditions. 1. peak-to-peak jitter after applying system transfer function fo r the common clock architecture. maximum limit for pci express gen 1. 2 . rms jitter after applying the two evaluation bands to the two tr ansfer functions defined in the common clock architecture and reporting the worst case results for each evaluation band. maximum limit for pc i express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). 3. rms jitter after applying system transfer function for the co mmon clock architecture. this s pecification is based on the pci _express_base_r3.0 10 nov, 2010 specification, and is subject to change pending the final release version of the specification. 4. this parameter is guaranteed by char acterization. not tested in production. table 21: jitter specifications 1,2,3 symbol parameter conditions min typ max pcie industry specification units notes t j (pcie gen1) phase jitter peak-to-peak ? = 100mhz, 25mhz input evaluation band: 0hz - nyquist (clock frequency/2) 30 86 ps 1,4 t refclk_hf_rms (pcie gen2) phase jitter rms ? = 100mhz, 25mhz input high band: 1.5mhz - nyquist (clock frequency/2) 2.56 3.10 ps 2,4 t refclk_lf_rms (pcie gen2) phase jitter rms ? = 100mhz, 25mhz input low band: 10khz - 1.5mhz 0.27 3.0 ps 2,4 t refclk_rms (pcie gen3) phase jitter rms ? = 100mhz, 25mhz input evaluation band: 0hz - nyquist (clock frequency/2) 0.8 1.0 ps 3,4 parameter symbol test condition min typ max unit oc-12 random jitter (12 khz?5 mhz) j oc12 clkin = 19.44 mhz, all clkn at 155.52 mhz 5 - 0.69 0.95 ps pci express 1.1 common clocked total jitter 6 -9.112ps rms jitter 6 , 10 khz to 1.5mhz - 0.1 0.3 ps rms jitter 6 , 1.5mhz to 50mhz - 0.9 1.1 ps pci express 3.0 common clocked rms jitter 6 -0.20.4ps notes : 2 for best jitter performance, keep the single ended clock input slew rates at more than 1.0 v/ns and the differential clock inp ut slew rates more than 0.3 v/ns. 3 all jitter data in this table is based upon all output formats being differential. when single-ended outputs are used, there i s the potential that the output jitter may increase due to the nature of single-ended outputs. if your configuration implements any single-ended output and any output is required to have jitter less than 3 ps rms, contact idt for support to validate your configuration and ensure the best jitter performance. in many configurations, cmos outputs hav e little to no effect upon jitter. 4 dj for pci and gbe is < 5 ps pp. 5 output fod in integer mode. 6 all output clocks 100 mhz hcsl format. jitter is from the pcie jitter filter combination that produces the highest jitter. jit ter is measured w ith the intel clock jitter tool, ver. 1.6.6. pci express 2.1 common clocked (vddx = 3.3v+5% or 2.5v+5%, ta = -40c to +85c) 1 all measurements w ith spread spectrum off.
march 3, 2017 17 progra mmable clock generator 5p49v5943 datasheet table 22: spread spectrum ge neration specifications test circuits and loads test circuits and loads for outputs symbol parameter description min typ max unit f out output frequency output frequency range 5300mhz f mod mod frequency modulation frequency 30 to 63 khz f spread spread value amount of spread value (programmable) - center spread 0.25% to 2.5% %f out amount of spread value (programmable) - down spread -0.5% to -5% outx v dda clk out gnd c l 0.1f v ddox 0.1f v ddd 0.1f 33 hcsl output 33 50 50 hcsl differential output test load 2pf 2pf zo=100ohm differential
programmable cloc k generator 18 march 3, 2017 5p49v5943 datasheet typical phase noise at 100mhz (3.3v, 25c) note : all outputs operational at 100mhz , phase noise plot with spurs on.
march 3, 2017 19 progra mmable clock generator 5p49v5943 datasheet 5p49v5943 appli cation schematic the following figure shows an example of 5p49v5943 application sch ematic. input and output terminati ons shown are intended as e xamples only and may not represent the exact user configuration. in this exam ple, the device is operated at v ddd, v dda = 3.3v. the decoupling capacitors should be located as close as possible to the power pin. as with any high speed analog circuitry, the power supply pins ar e vulnerable to random noise. to achieve optimum jitter perfor mance, power supply isolation is required. 5p49v5943 provides separate power supplies to isolate any high switching noise from coupling into the internal pll. in order to achieve the best possible filtering, it is recomme nded that the placement of the fi lter components be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pin filter should be placed on t he device side. the other components can be on t he opposite side of the pcb. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devic es. the filter performance is designed for a wide range of noise frequencies. this low-pass filter starts to at tenuate noise at approximately 10 khz. if a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component value s be adjusted and if required, additio nal filtering be added. additionally, good general design practices for power plane voltage st ability suggests adding bulk capacitance in the local area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and fun ctional tables in the datasheet to ensure the l ogic control inputs are properly set.
programmable cloc k generator 20 march 3, 2017 5p49v5943 datasheet 5p49v5943 reference schematic 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 d d c c b b a a revision history 0.1 03/26/2015 first publication manufacture part number z@100mhz pkgsz dc res. current(ma) fair-rite 2504021217y0 120 0402 0.5 200 murata blm15ag221sn1 220 0402 0.35 300 murata blm15bb121sn1 120 0402 0.35 300 tdk mmz1005s241a 240 0402 0.18 200 tecstar tb4532153121 120 0402 0.3 300 note:ferrite bead fb1 = place near i2c controller if used lvds termination 3.3v lvpecl termination 2.5v and 3.3v hcsl termination configur ation pull-up for hardware control remove for i2c lvcmos termination for lvds, lvpecl ac couple use termination on right 5,6,7 and 20 pull-down resistors: have weak internal the following pins see datasheet for bias network layout notes: 1. route power from bead through bulk capacitor pad then through 0.1uf capacitor pad then to clock chip vdd pad. 2. do not share ground vias. one ground pin one ground via. v1p8vca out_0_sel-i2c clkin v1p8vc clkinb outr0 v1p8vc outr1 sda outrb1 scl v1p8vc outr2 sd/oe outrb2 sda scl clkin out_0_sel-i2c clkinb v1p8vca outr2 out_2 v1p8vc v1p8vca vcc1p8 v3p3 v1p8vc size document number re v date: sheet of 0.1 integrated device technology a 11 thursday, march 26, 2015 5p49v5943a_sch san jose, ca size document number re v date: sheet of 0.1 integrated device technology a 11 thursday, march 26, 2015 5p49v5943a_sch san jose, ca size document number re v date: sheet of 0.1 integrated device technology a 11 thursday, march 26, 2015 5p49v5943a_sch san jose, ca r3 100 1 2 u2 receiver 1 2 c11 .1uf 1 2 r9 10k 1 2 r12 50 1 2 c8 .1uf 1 2 c4 .1uf 1 2 c5 .1uf 1 2 r2 2.2 1 2 r5 49.9 1% 1 2 u5 5p49v5943a vdda 3 vdd 4 clkin 1 clkinb 2 sel1/sda 6 sel0/scl 7 sd/oe 5 vddd 17 vddo0 19 out0_sel_i2cb 20 vddo1 15 out1 14 out1b 13 vddo2 8 out2 9 out2b 10 gnd 12 gnd 11 epad 21 epad 22 epad 23 epad 24 epad 25 gnd 16 gnd 18 u4 receiver 1 2 c13 .1uf 1 2 r14 33 1 2 r10 50 1 2 r11 50 1 2 r8 10k 1 2 c3 .1uf 1 2 r6 33 1 2 r4 49.9 1% 1 2 r15 33 1 2 c1 10uf 1 2 r13 33 1 2 c2 1uf 1 2 r7 10k 1 2 fb1 signal_bead 1 2 c12 .1uf 1 2 u3 receiver 1 2
march 3, 2017 21 progra mmable clock generator 5p49v5943 datasheet clkin equivalent schematic figure clkin equivalent schematic below shows the basis of the requirements on vih max, vil min and the 1200 mv p-p single ended vswing maximum. ? the clkin and clkinb vih max spec comes from the cathode voltage on the input esd diodes d2 and d4, which are referenced to the intern al 1.2v supply. clkin or clkinb voltages greater than 1.2v + 0.5v =1.7v will be clamped by these diodes. clkin and clkinb input voltages less than -0.3v will be clamped by diodes d1 and d3. ? the 1.2v p-p maximum vswing input requirement is determined by the internally regulated 1.2v supply for the actual clock receiver. this is th e basis of the vswing spec in table 13. clkin equivalent schematic
programmable cloc k generator 22 march 3, 2017 5p49v5943 datasheet wiring the differential input to accept single-ended levels figure recommended schematic for wiring a differential input to accept single-ended levels shows how a differential input can be wired to accept single ended levels. this configuration has three properties; the total output impedance of ro and rs matches the 50 ohm transmission line impedance, the vrx voltage is generated at the clkin inputs which maintains the lvcmos driv er voltage level across the transmission line fo r best s/n and the r1-r2 voltage divider values ensure that vrx p-p at clkin is less than the maximum value of 1.2v. recommended schematic for wiring a differential input to accept single-ended levels table 23 nominal voltage divider values vs driver vdd shows resistor values that ensu re the maximum drive level for the clkin port is not exceeded for all combinations of 5% tolerance on the driver vdd, the versaclock vddo_0 and 5% resistor tolerances . the values of the resistors can be adjusted to reduce the loading for slower and weaker lvcmos driver by increasing the impedance of the r1-r2 divider. to assist this assessmen t, the total load on the driver is included in the table. table 23: nominal voltage di vider values vs driver vdd ? r1 r2 vrx versaclock 5 receiver clki n clki nb lv cmos vdd zo = 50 ohm ro + rs = 5 0 rs ro lvcmos driver vdd ro+rs r1 r2 vrx (peak) ro+rs+r1+r2 3.3 50.0 130 75 0.97 255 2.5 50.0 100 100 1.00 250 1.8 50.0 62 130 0.97 242
march 3, 2017 23 progra mmable clock generator 5p49v5943 datasheet hcsl differential clock input interface clkin/clkinb will accept dc coupled hcsl signals. clkin, clkinb input driven by an hcsl driver 3.3v differential lvpecl clock input interface the logic levels of 3.3v l vpecl and lvds can exceed vih max for the clkin/b pins. theref ore the lvpecl levels must be ac coupled to the versaclock differential input and the dc bias restored with external voltage dividers. a single table of bias resistor values is prov ided below for both for 3.3v lvpecl and lvds. vbias can be vddd, v ddox or any other available voltage at the versaclock receiver that is most conveniently access ible in layout. clkin, clkinb input driven by a 3.3v lvpecl driver zo=50ohm zo=50ohm clkin clkinb versaclock 5 receiver q nq +3.3v lvpecl driver zo=50ohm zo=50ohm versaclock 5 receiver r9 r10 50ohm 50ohm vbias rpu1 rpu2 clkin clkinb rtt 50ohm c5 0.01f c6 0.01f r15 4.7kohm r13 4.7kohm
programmable cloc k generator 24 march 3, 2017 5p49v5943 datasheet clkin, clkinb input driven by an lvds driver table 24: bias resistors for 3.3v lv pecl and lvds drive to clkin/b 2.5v differential lvpecl clock input interface the maximum dc 2.5v lvpecl voltage meets the vih max clkin requirement. therefore 2.5v lvpecl can be connected directly to the clki n terminals with out ac coupling clkin, clkinb input driven by a 2.5v lvpecl driver vbias (v) rpu1/2 (kohm) clkin/b bias voltage (v) 3.3 22 0.58 2.5 15 0.60 1.8 10 0.58 lvds driver zo=50ohm zo=50ohm versaclock 5 receiver rterm 100ohm vbias rpu1 rpu2 clkin clkinb c1 0.1f c2 0.1f r1 4.7kohm r2 4.7kohm +2.5v lvpecl driver zo=50ohm zo=50ohm r1 r2 50ohm 50ohm rtt 18ohm versaclock 5 receiver clkin clkinb
march 3, 2017 25 progra mmable clock generator 5p49v5943 datasheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? . and 132 ? . the actual value should be select ed to match the differential impedance (zo) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? . differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the rece iver as possible. the standard termination schematic as shown in figure standard termination or the termination of figure optional termination can be used, which uses a center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. in addition, since these outputs are lvds compatible, the input receiver's amplitude and common-mode input range should be verified for compatibilit y with the idt lvds output. if using a non-standard termination, it is recommended to contact idt and confirm that the termination will function as in tended. for ex ample, the lvds outputs cannot be ac coupled by placing capacitors between the lvds outputs and the 100 ohm shunt load. if ac coupling is required, the coupling caps must be placed between the 100 ohm shunt termination and the receiver. in this manner the termination of the lvds output remains dc coupled. lvds driver lvds driver lvds receiver lvds receiver z t c z o ? z t z o ? z t z t 2 z t 2 standard termination optional termination
programmable cloc k generator 26 march 3, 2017 5p49v5943 datasheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc cu rrent path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. the figure below show two different layo uts which are recommended only as guidelines. other suitab le clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3v lvpecl output termination (1) 3.3v lvpecl output termination (2) lvpecl zo=50ohm zo=50ohm 3.3v r1 r2 3.3v 50ohm 50ohm rtt 50ohm input + - lvpecl zo=50ohm zo=50ohm 3.3v + - input r1 r2 3.3v 84ohm 84ohm 3.3v r3 r4 125ohm 125ohm
march 3, 2017 27 progra mmable clock generator 5p49v5943 datasheet termination for 2.5v lvpecl outputs figures 2.5v lvpecl driver termi nation example (1) and (2) show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v ddo ? 2v. for v ddo = 2.5v, the v ddo ? 2v is very close to ground level. the r3 in figure 2.5v lvpecl driver termination example (3) can be eliminated and the termination is shown in example (2). 2.5v lvpecl driver termination example (1) 2.5v lvpecl driver termination example (2) 2.5v lvpecl driver termination example (3) 2.5v lvpecl driver zo=50ohm zo=50ohm 2.5v + - r2 r4 v ddo = 2.5v 62.5ohm 62.5ohm 2.5v r1 r3 250ohm 250ohm 2.5v lvpecl driver zo=50ohm zo=50ohm 2.5v + - r1 r2 v ddo = 2.5v 50ohm 50ohm 2.5v lvpecl driver zo=50ohm zo=50ohm 2.5v + - r1 r2 v ddo = 2.5v 50ohm 50ohm r3 18ohm
programmable cloc k generator 28 march 3, 2017 5p49v5943 datasheet pci express application note pci express jitter analysis me thodology models the system response to reference clock jit ter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase interpolator in the receiver. these transfer functi ons are called h1, h2, and h3 respectively. the overall syste m transfer function at the receiver is: the jitter spectrum seen by the receiver is the result of applying this system transfer fu nction to the clock spectrum x(s) and is: in order to generate time doma in jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen1 magnitude of transfer function for pci express gen2, two transfer functions are defined with 2 evaluation ranges and the final jitte r number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen2a magnitude of transfer function pcie gen2b magnitude of transfer function for pci express gen 3, one trans fer function is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. ht s ?? h3 s ?? h1 s ?? h2 s ?? ? ?? ? = ys ?? xs ?? h3 s ?? ? h1 s ?? h2 s ?? ? ?? ? =
march 3, 2017 29 progra mmable clock generator 5p49v5943 datasheet pcie gen3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference clock requirements. marking diagram 1. ?ddd? denotes dash code. 2. line 2: truncated part number 3. ?yw? is the last digit of the year and week that the part was assembled. 4. ? ** ? denotes sequential lot number. 5. ?$? denotes mark code. ddd 5943b yw**$
programmable cloc k generator 30 march 3, 2017 5p49v5943 datasheet package outline and dimensions (20-pin 3 x 3 mm vfqfpn)
march 3, 2017 31 progra mmable clock generator 5p49v5943 datasheet package outline and dimensions (20-pin 3 x 3 mm vfqfpn), cont.
programmable cloc k generator 32 march 3, 2017 5p49v5943 datasheet ordering information note: ?ddd? denotes the dash code. ?g? after the two-letter package code denote s pb-free configuration, rohs compliant. revision history part / order number marking shipping packaging package temperature 5P49V5943BDDDNDGI see page 29 trays 20-pin vfqfpn -40 to +85 ? c 5P49V5943BDDDNDGI8 tape and reel 20-pin vfqfpn -40 to +85 ? c date description of change march 3, 2017 updated po ds and legal disclaimer february 24, 2017 1. added ?out put alignment? section. 2. update ?output divides? section.
disclaimer integrated device technology, in c. (idt) and its affiliated companies (herei n referred to as ?idt?) reserve the righ t to modify the products and/or specificat ions described herein at any time, without notice, at idt?s sole discretion. perfor mance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is prov ided without representation or wa rranty of any kind, whether expr ess or implied, including, but not limited to, the suitab ility of idt's products for any particular purpose, an implied warranty of merchantability, or non-infri ngement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intel- lectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datashee t type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology , inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales tech support www.idt.com/go/support

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